1. Field of the Invention
The present invention is related to a method of forming a finFET device, and particularly, to a method of forming a self-aligned finFET device.
2. Description of the Prior Art
Dynamic random access semiconductor memory (DRAM) is comprised of memory cells, and the memory cells are electrically connected by word lines in the horizontal direction and are electrically connected by bit lines in the horizontal direction. By means of activating specific word lines or bit lines, data are read from or stored into the memory cells. Commonly speaking, each memory cells include a selection transistor and a storage capacitor. The selection transistor is a field-effect transistor (FET) of a lateral structure having two diffusion areas that are separated by a channel. In addition, a gate is formed on the channel. The word line connects the gate and one of the diffusion areas. The other diffusion area is connected to the storage capacitor. When a bias is applied to the gate through the word line, the selective transistor is activated and introduces a current into the diffusion areas. The storage capacitor is also charged by the bit line.
A finFET device of higher integrity and higher performance is disclosed to lend itself to become better suited for use in the current electronic product trend of miniaturization. The existing finFET device is an advanced device which is originated from the conventional standard-typed FET. The gate of the conventional FET switches the circuit on and off at only one side to allow the conduction of current. On the other hand, the gate of the finFET device is formed as a fin to switch the circuit at both sides of the gate. The finFET device operates the circuit more easily and has advantages such as shorter leakage path in the substrate, higher driving current, and lower short channel effect. In addition, the development of the finFET device is able to reduce the volume of the FET, increase the density of the finFET device on the wafer, improve the yield of the chips fabricated from each wafer, and effectively reduce production costs.
Conventional method for forming finFET devices is performed on a semiconductor substrate. Several processes are preformed for forming the finFET devices, which includes a etch process, a deposition process, a CMP process, and an ion implantation process to define an active area, a plurality of trench capacitors, a gate area, a drain area, and a source area disposed between the trench capacitors. A top trench oxide layer covers each of the trench capacitor. In order to form a narrow fin structure, a hard mask or a photoresist layer is formed on the surface of the semiconductor layer. Then, a lithography and etch process is performed to define an opening on the hard mask or the photoresist layer for exposing a part of the gate area and defining the position and the width of the fin structure. Followed by subsequent etch processes, a narrow fin structure is formed in the gate area.
However, the above-mentioned method for forming finFET devices has many defects that are needed to be improved and to be overcome. For example, the existing method for forming a fin structure of a finFET device is performed by means of performing several lithography and etch processes to define the gate structure. It is difficult to precisely sculpt the outline of the fin structure of the finFET device. In addition, CD variation of the fin structure of the finFET device is difficult to be controlled within the tolerance range when the fin structure of the finFET device is formed under a 70-nanometer process. As a result, a short circuit may occur between the finFET devices.